(a) Field of the Invention
The present invention relates to a plasma display panel (PDP). More specifically, the present invention relates to an address driver circuit for applying an address voltage.
(b) Description of the Related Art
In recent years, flat panel displays such as a liquid crystal display (LCD), a field emission display (FED), a PDP, and the like have been actively developed. The PDP is advantageous over the other flat panel displays in regard to its high luminance, high luminous efficiency, and wide view angle, and accordingly, it is favorable for making a large-scale screen of more than 40 inches as a substitute for the conventional cathode ray tube (CRT).
The PDP is a flat panel display that uses plasma generated by gas discharge to display characters or images and includes, according to its size, more than several scores to millions of pixels arranged in a matrix pattern. Such a PDP is classified into a direct current (DC) type and an alternating current (AC) type according to its discharge cell structure and the waveform of the driving voltage applied thereto.
The DC-type PDP has electrodes exposed to a discharge space, allowing a DC to flow through the discharge space while voltage is applied, and hence requires resistors for limiting the current. The AC-type PDP has electrodes covered with a dielectric layer that naturally forms a capacitance component that limits the current and protects the electrodes from the impact of ions during a discharge. Thus the AC-type PDP is superior to the DC-type PDP in regard to long lifetime.
The AC type-PDP has scan and sustain electrodes and address electrodes. The scan and sustain electrodes are formed in parallel with each other on one side of the PDP, and the address electrodes are formed on the other side of the PDP and are perpendicular to the scan and sustain electrodes. The sustain electrodes are formed in correspondence to the scan electrodes with one terminal thereof commonly coupled to one terminal of each scan electrode.
Typically, the driving method of the AC-type PDP is sequentially composed of a reset step, an addressing step, a sustain discharge step, and an erase step.
In the reset step, the state of each cell is initialized in order to readily perform an addressing operation on the cell. In the addressing step, an address voltage is applied to accumulate wall charges on selected “on”-state cells and other “on”-state cells (i.e., addressed cells) for selecting “off”-state cells on the panel. In the sustain step, a sustain discharge voltage pulse is applied so as to cause a discharge that actually displays an image on the addressed cells. In the erase step, the wall charges on the cells are erased to end the sustain discharge.
In the AC-type PDP, the discharge spaces formed between the scan and sustain electrodes and between the address electrode side and the scan/sustain electrode side act as a capacitive load (hereinafter referred to as “panel capacitor”) so that capacitance exists on the panel. Due to the capacitance of the panel capacitor, a reactive power is required in addition to the addressing power in order to apply a waveform for an addressing operation. Typically, the address driver circuit for a PDP includes a power recovery circuit for recovering the reactive power and reusing it. The power recovery circuits are suggested in U.S. Pat. Nos. 4,866,349 and 5,081,400 by L. F. Weber.
With the conventional power recovery circuit mounted on an address buffer board, a conductive output pattern running in the transverse direction of the address buffer board may cause a parasitic inductance component. More specifically, a plurality of address driving ICs are required for driving the address electrodes, because all the address electrodes cannot be coupled to a single address driving IC. By using one power recovery circuit for the plural address driving ICs, the parasitic inductance component is possibly formed on the output pattern in which the address driving ICs are coupled to the address buffer board. The parasitic inductance component causes an extreme distortion on the address driving waveform. Namely, an undesired pulse rise may occur in the rise/drop interval of the address driving waveform because of the parasitic inductance component.